EC340 Computer Architecture 3 (3+0)
BS Computer Engineering Program
UPDATED NEWS...
 Quiz 3 solution uploaded.
 Lecture 10 'Pipelined Processors' has uploaded.
Course Information
Semester 
5th Semester  Fall 2017 
Prerequisite 
EC224 Computer Organization, EC121 Digital Logic Design 
Course Instructor/s 
Dr Hashim Ali 
Email 
hashim.ali@hitecuni.edu.pk 
Teaching Assistant (TA) 
Sana Naseer [text] 
Office Hours 
Friday, 02:00  04:00
Appointment by email

Text Book/s
 David A. Patterson, John L. Hennesy, "Computer Organisation and Design: The Hardware/Software Interface", 5th edition, Morgan Kaufmann, 2013, ISBN: 9780124077263. [Download]
 William Stallings, "Computer Organisation and Architecture", 10th edition, Pearson, 2016, ISBN: 9780134101613. [Download]
 David A. Patterson, John L. Hennessy, "Computer Architecture: A Quantitative Approach", 5th edition, Morgan Kaufmann, 2017, ISBN: 9780128119051. [Download]
Course Objective
Upon completion of this course, the student will have basic understanding of computer system architecture including CPU design, memory subsystem design and performance enhancement techniques.
ESSENTIAL TOPICS TO BE COVERED:
 Processor systems design
 Memory subsystem design
 Device subsystems
 Performance enhancement techniques
 Parallel architectures
Course Contents
Overview of main computer architectures and quantitative analysis of merits and pitfalls in computer performance, instruction set architecture, binary arithmetic and ALU design (adder, multiplier, divider), speedingup addition/subtraction and multiplication/division, Floating point representation and FPU design, CPU design, singlecycle processor design (datapath + control), multicycle processor design (datapath + control), microcodes, microprogrammed control, analysing single/multicycle performance w.r.t CPI, pipeline processor and hazards, branch prediction, instruction level parallelism (ILP), introduction to parallel processing.
Program Learning Outcomes
 PLO 1. Engineering Knowledge: An ability to apply knowledge of mathematics, science, engineering fundamentals and an engineering specialization to the solution of complex engineering problems.
 PLO 2. Problem Analysis: An ability to identify, formulate, research literature, and analyse complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences and engineering sciences.
 PLO 3. Design/Development of Solutions: An ability to design solutions for complex engineering problems and design systems, components or processes that meet specified needs with appropriate consideration for public health and safety, cultural, societal, and environmental considerations.
 PLO 10. Communication: An ability to communicate effectively, orally as well as in writing, on complex engineering activities with the engineering community and with society at large, such as being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.
Course Learning Outcomes
 CLO 1. Demonstrate how to add, subtract, multiply, divide integers and floatingpoint numbers using 2's complement and IEEEFloating point representations and their digital circuit design. [Cognitive, C2].
 CLO 2. Analyse clock periods, performance and instruction throughput of singlecycle, multicycle and pipelined implementation of a simple instruction set. [Cognitive, C4].
 CLO 3. Design basic and intermediate RISC processor (single cycle, multicycle) including instruction sets, data paths, microprogrammed control and ways of dealing with pipeline hazards. [Cognitive, C5].
 CLO 4. Develop basic simulator and communicate findings on processor design. [Affective, A4].
Grading Policy
75% class attendance is mandatory to appear in the examination. Course grades will be determined by the following weights:
Marks Distribution 
Assignment/Project 
10% 
Quizzes 
10% 
Sessional  I 
20% 
Sessional  II 
20% 
Final Exam 
40% 
Course Total 
100% 
NOTE:
 Missed Class: If you miss a class, it is your responsibility to get the homework assignment or handout from your classmates. More importantly, you make an effort to understand the material covered in class.
 Late Work: The penalty for any late work is 20% off for the first date and an additional 30% off for the second day. No work will be accepted thereafter.
Schedule of Exams
 Commencement of Classes : September 18, 2017
 SessionalI : October 30 to November 03, 2017
 SessionalII : December 11 to December 15, 2017
 Final Exam : January 22 to January 27, 2018
 Results Notification : , 2017
Download Course Outline
Lectures Plan
Reading material about topics related to the course is mentioned under "Support Documents, Resources, and Links".
Week# Date 
Topic 
Slide Download Link 
Readings 
Evaluation 
1 19, 21/9/17 
Introductory Lecture 
Lecture 0 
 
 
2 28, 29/9/17 
Appendix J Computer Arithmetic 
Lecture 1 Appendix J 
Ch 9,10Stalligs Appendix JHennessy 
 
3 4, 5/10/17 
Instruction Set ArchitectureI

Lecture 2 [Updated on 19/10] 
Ch 11,12Stalligs Design Simple Microprocessor 
Quiz 1 
4 11, 12/10/17 
Instruction Set ArchitectureII & III

 
 
 
5 18, 19/10/17 
Architectural Space

Lecture 3 
 
 
6 25, 26/10/17 
Performance

Lecture 4 
Ch 1Hennessy 
 
7 30/1003/11/17 
Sessional  I Exam 
8 8, 9/11/17 
ALU Design Binary Arithmetic Comparison Logical Operations Signed Operations Overflow 
Lecture 5 
 
 
9 15, 16/11/17 
ALU Design Multiplier Design Divider Design 
Lecture 6 
Signed Binary Division Rules [pdf] 
 
10 22, 23/11/17 
ALU Design Speeding up Addition/Subtraction Floatingpoint Representation Floatingpoint Unit Design 
Lecture 7 IEEE 754 Calculator 
 
Quiz 2 
11 29, 30/11/17 
Remaining Lecture 7 Processor Design Introduction Signle Cycle Design (Datapath + Control) Analysing Perfromance 
Lecture 8 
Ch 4 & Appendix_B  Hennessy 
 
12 6, 7/12/17 
Remaining Lecture 8 
 
Ch 4 & Appendix_B  Hennessy 
Assignment 1  Deadline 
13 1115/12/17 
Sessional  II Exam 
14 19, 21/12/17 
Processor Design Multicycle Design (Datapath) 
Lecture 9 
 
 
15 26, 28/12/17 
Processor Design Multicycle Design (Control) 
 
 
 
16 2, 4/1/18 
Processor Design Microprogrammed Control 
 
 
 
17 9, 11/1/18 
Pipelined Processor Design Pipelining Types of Pipelining Hazards (Structural, Data, Control) 
Lecture 10 
 
Quiz 3 
18 16, 18/1/18 
Remaining Lecture 10 
 
 
Quiz 4 Assignment 2  Deadline 
19 2227/1/18 
Final Exam 
Assignments
Download Assignment Cover Page
 Assignment 1  Deadline December 09, 2017  Submission Link
 4bit ALU  Logisim files  Deadline November 30, 2017  Submission Link
Quizzes
Try to cover the course material everyday!! Surprise quizzes may be taken during the course.
 Quiz 1 Solution (pdf)
 Quiz 2 Solution (pdf)
 Quiz 3 Solution (pdf)
Exams
Software Links
 Online MIPS Emulator: Visual MIPS [Link]
 A Visual MIPS R2000 Processor Simulator  Freeware  ProcSim
 IEEE 754 Floating Point Calculator [Link]
Support Documents, Resources, and Links
Class Standings
Class Attendance
Attendance Sheet
Class Grades
Grades Sheet