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Semester  3rd Semester  Fall 2017 

Prerequisite  Programming Fundamentals 
Course Instructor/s  Dr Hashim Ali 
Lab Instructor/s  Ms Kayynat Rana, Ms Sadia Azam 
hashim.ali@hitecuni.edu.pk, sadia.azam@hitecuni.edu.pk  
Teaching Assistant (TA)  Sana Naseer [text] 
Office Hours 

Text Book/s
To introduce the basic knowledge of Boolean algebra, design and analysis of Combinational Logic Circuits, design and analysis of Sequential Logic Circuits, Registers, Counters, Memory and programmable logic devices.
Introduction, number systems, Boolean algebra, logic gates (AND, OR, NOT etc.), Karnaugh maps, QM method, combinational circuits, half & full adder and subtractor, comparator, encoders, decoders, multiplexer, demultiplexer, sequential circuits, Flip Flop, (RS, JK, D, T, Master Slave), state transition diagram, counters, registers, memories, PLAs, Programmable Logic Devices (PLDs), hardware descriptive language (HDL Verilog), lab assignments using tools such as Verilog HDL/VHDL, Logisim, etc.
Design and simulation of logic circuits through Logisim and Verilog, Basic logic gates, hardware implementation of combinational logic circuits such as multiplexers and demultiplexers, encoders/decoders, ALU; implementation of sequential circuits such as flipflops, registers, shift registers, counters and other digital circuits.
75% class attendance is mandatory to appear in the examination. Course grades will be determined by the following weights:
Theory (70%)  Laboratory (30%)  

Assignments  2%  Lab Reports  5% 
Quizzes  10%  Lab Performance  15% 
Sessional  I  10%  Viva Voce  10% 
Sessional  II  10%     
Final Exam  38%  
Course Total (100%)  Theory (70%) + Laboratory (30%) 
NOTE:
Reading material about topics related to the course is mentioned under "Support Documents, Resources, and Links".
Week# Date  Topic  Slide Download  Readings  Evaluation 
1 18, 20/9/17  Introduction to Digital Systems Number Systems Decimal, Binary, Octal, Hexadecimal 
Lecture 1  Ch 1.11.6 Mano Ch 2 Floyd 
 
2 25, 28/9/17  Number Systems Signed Numbers Complements Computer Arithmetic Binary Codes 
Lecture 2  Ch 1.11.6 Mano Ch 2 Floyd 
 
3 5, 7/9/17  Boolean Algebra and Logic Gates Basic Definitions Boolean Algebra [Theorems, Properties] Boolean Functions Canonical and Standard Forms Digital Circuit Optimization 
Lecture 3  Ch 2 Mano Ch 3, 4.14.7 Floyd 
Quiz 1 
4 9, 12/9/17  Remaining Lecture 3 Gatelevel Minimization The Map Method 
  Ch 3.1 Mano  Quiz 2 
5 16, 19/9/17  Gatelevel Minimization Two/Three/Fourvariable KMaps ProductofSums Simplification Don'tcare Conditions NAND and NOR Implementaiton ExclusiveOR Function 
Lecture 4 Lecture 5 
Ch 3.23.4 Mano Ch 4.84.11 Floyd 
 
6  Revision 
    Quiz 3 Assignment 1  Deadline 
7 30/1003/11/17  Sessional  I Exam  
8 06, 09/11/17  Combinational Logic  I Intro to Combinational Circuits Design Procedure Binary AdderSubtractor Decimal Adder Binary Multiplier Magnitude Comparator 
Lecture 6  Ch 4.14.8 Mano   
9 13, 16/11/17  Combinational Logic  II Decoders Encoders Multiplexers 
Lecture 7  Ch 4.9 Mano  Quiz 4 
10 20, 23/11/17  Revision      Quiz 5 
11 27, 30/11/17  Combinational Logic  II Encoders Multiplexers 
Remaining Lecture 7  Ch 4.104.11 Mano   
12 04, 07/12/17  Combinational Logic Excercises 
     
13 11, 15/12/17  Sessional  II Exam  
14 18, 21/12/17  Demonstration of Lab Experiment Synchronous Sequential Logic Introduction 
Lecture 8  Ch 5.15.2 Mano   
15 25, 28/12/17  Synchronous Sequential Logic Storage Elements  Latches and FlipFlops 
  Ch 5.35.4 Mano   
16 1, 4/1/18  Synchronous Sequential Logic Analysis of Sequential Circuits State Reductions and Assignments 
  Ch 5.5, 5.7 Mano   
17 8, 11/1/18  Synchronous Sequential Logic Design of Sequential Circuits Counters Design 
Lecture 9  Ch 5.8 Mano  Quiz 6 
18 15, 1871/18      Assignment 2  Deadline  
19 2227/1/18  Final Exam 
Download Assignment Cover Page
Try to cover the course material everyday!! Surprise quizzes may be taken during the course.
Week#  Experiment Title  Mannual Download  Mannual Upload Only ZIP file 

1  Introduction to Digital Logic Trainer and Logic Gates.  Lab 1  Sec A   Sec B  
2  Implementation of Boolean Functions on Digital Trainer.  Lab 2  Sec A   Sec B  
3  Verilog Implementation of basic logic gates and Boolean functions.  Lab 3  Sec A   Sec B  
4  Introduction to Digital Logic Circuit Simulation with Logisim.  Lab 4  Sec A   Sec B  
5  The objective of this lab is to familiarize students how to obtain simplest implementation of any digital circuit.  Lab 5  Sec A   Sec B  
6  Implementation of Half and Full Adders.  Lab 6  Sec A  link  Sec B  link 
7  Simulation of 4bit Adder/Subtractor using Logisim and Implementation on Verilog using Hierarichal Design.  Lab 7  Sec A  link  Sec B  link 
8  Resubmit the complete 4bit Adder/Subtrator Logisim circuit and Verilog Code.  Lab 8  Sec A  link  Sec B  link 
9  Design and Implementation of 2x4 and 3x8 decoder and Verilog Implementation.  Lab 9  Sec A  link  Sec B  link 
10  Design and Implementation of 2x1 and 4x1 multiplexer and Verilog Implementation.  Lab 10  Sec A  link  Sec B  link 
11  Understanding the behaviour of 4bit Adder/Subtractor using integration of various combinational circuit components.  Lab 11  Sec A  link  Sec B  link 
12  Implementation of magnitude comparator and verilog data flow modeling.  Lab 12     
13  .       
14  Implementation of Counter Circuit using D Flip Flop.  Lab 14     